Method and structure for controlling bandwidth and peaking over gain in a variable gain amplifier (VGA)

ABSTRACT

A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to “tune” the bandwidth and peaking in a communication system.

CROSS-REFERENCES TO RELATED APPLICATIONS

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BACKGROUND OF THE INVENTION

The present invention relates to communication systems and integratedcircuit (IC) devices. More particularly, the present invention providesfor improved methods and devices for controlling bandwidth and peakingover gain in a variable gain amplifier (VGA).

Over the last few decades, the use of communication networks exploded.In the early days Internet, popular applications were limited to emails,bulletin board, and mostly informational and text-based web pagesurfing, and the amount of data transferred was usually relativelysmall. Today, Internet and mobile applications demand a huge amount ofbandwidth for transferring photo, video, music, and other multimediafiles. For example, a social network like Facebook processes more than500 TB of data daily. With such high demands on data and data transfer,existing data communication systems need to be improved to address theseneeds.

Amplifiers are commonly used as stages in communication systems to boostsignals by a gain factor before outputting the signal to another stage.Typical applications of such amplifiers require control over bandwidthand peaking to maintain performance within target specifications.However, as systems include more and more stages, it becomes difficultto control the bandwidth and peaking of an amplifier stage.

Contemporary amplifiers have been inadequate for controlling bandwidthand peaking. Therefore, improved amplifier structure and methods,including improved methods of controlling bandwidth and gain, are highlydesired.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to communication systems and integratedcircuit (IC) devices. More particularly, the present invention providesfor improved methods and devices for controlling bandwidth and peakingover gain in a variable gain amplifier (VGA).

A “full” Gilbert cell, also known as a four quadrant multiplier, is aconventional cross-coupled differential amplifier often used in radiofrequency (RF) integrated circuits. Common applications of such cellsinclude mixers, automatic gain control (AGC) amplifiers, amplitudemodulators, double sideband (DSB) modulators, single sideband (SSB)modulators, AM detectors, SSB and DSB detectors, frequency doublers,squaring circuits, dividers, square-root circuits, root-mean-squaremeasuring circuits, and the like. There are also “half” Gilbert cells,also known as two quadrant multipliers. However, even conventionalGilbert cells have difficulty controlling bandwidth and peaking whenintegrated into a system with many other stages.

The present invention provides a modified Gilbert cell structure forimproved control of bandwidth and peaking over gain in variable gainamplifier (VGA). The device receives a differential input signal havinga first input signal and a second input signal; and a differential biassignal having a first bias signal and a second bias signal. In aspecific example, the differential input signal can be a differential RFinput signal. The differential bias signal can be a differential localoscillator (LO) signal or a static differential signal. Further, thedifferential bias signal controls the gain of the Gilbert cell thatamplifies the differential RF input signal.

The device includes at least three differential transistor pairs. Thefirst differential transistor pair includes transistors denoted T1 andT2. Each transistor includes a first node, a second node, and a thirdnode; wherein the third nodes of each transistor in the pair areelectrically coupled together. A first load resistor is electricallycoupled to the second node of T2 and a first load node. A first loadinductor is electrically coupled to the first load node and a powersupply rail.

The second differential transistor pair include transistors denoted T3and T4. Similarly, each transistor includes a first node, a second node,and a third node; wherein the third nodes of each transistor in the pairare electrically coupled together. Also, the load configuration issimilar with a second load resistor electrically coupled to the secondnode of T3 and a second load node, as well as and a second load inductorelectrically coupled to the second load node and the power supply rail.

The cross-coupling configuration is such that the second node of T4 iselectrically coupled to the first load node and the second node of T1 iselectrically coupled to the second load node. The second node of T2 andthe second node of T3 form differential output nodes. Traditionally, thecurrent components that run through T1 and T4 are “dumped” to the powersupply rail. With the load resistors and load inductors, thisconfiguration results in a “half” Gilbert configuration on each of theload resistors and a “full” Gilbert configuration on each of the loadinductors. The result is higher bandwidth and peaking at high gaincompared to low gain.

Each component of the differential input signal is fed into onetransistor of each of the two differential transistor pairs in thecross-coupled configuration. The first node of T2 is electricallycoupled to the first node of T3, and the first input signal iselectrically coupled to the first node of T2 and the first node of T3.The first node of T1 is electrically coupled to the first node of T4,and the second input signal is electrically coupled to the first node ofT1 and the first node of T4.

The third differential pair provides the input signal in differentialcurrent form for the cross-coupled differential pairs discussedpreviously. The third differential transistor pair includes transistorsdenoted T5 and T6, and, similar to the other pairs, each transistorincludes a first node, a second node, and a third node. Here, the thirdnodes of each transistor in the pair are electrically coupled to acurrent source node, and a current source is electrically coupledbetween the current source node and ground.

As discussed above, by cross coupling the T1 and T4 current to the loadinductors (i.e., “full” Gilbert configuration), the effect of the loadinductors is effectively reduced at low gain. In specific example, thetap point into the inductor can be chosen as another variable to “tune”the bandwidth and peaking over gain. When incorporated into a systemwith many stages, this “tuning” provides another means of mitigatingeffects on gain and peaking.

Many benefits are recognized through various embodiments of the presentinvention. Such benefits include improved control of bandwidth andpeaking over gain. In a specific example, the improved amplifierconfiguration results in higher bandwidth and peaking at high gain. Theeffects of this configuration can be used to mitigate the effects ofother stages in a communication system on bandwidth and peaking. Otherbenefits will be recognized by those of ordinary skill in the art thatthe mechanisms described can be applied to other communications systemsas well.

A further understanding of the nature and advantages of the inventionmay be realized by reference to the latter portions of the specificationand attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more fully understand the present invention, reference ismade to the accompanying drawings. Understanding that these drawings arenot to be considered limitations in the scope of the invention thepresently described embodiments and the presently understood best modeof the invention are described with additional detail through the use ofthe accompanying drawings in which:

FIG. 1 is a simplified circuit diagram of a variable gain amplifier(VGA) device according to an example of the present invention.

FIG. 2 is a simplified graph of gain (A) and effective load inductanceover current steering factor (a) illustrating the characteristics of aVGA device according to an example of the present invention.

FIG. 3 is a simplified graph illustrating a simulation of a VGA withgain dependent inductive peaking according to an example of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to communication systems and integratedcircuit (IC) devices. More particularly, the present invention providesfor improved methods and devices for controlling bandwidth and peakingover gain in a variable gain amplifier (VGA).

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

A “full” Gilbert cell, also known as a four quadrant multiplier, is aconventional cross-coupled differential amplifier often used in radiofrequency (RF) integrated circuits. Common applications of such cellsinclude mixers, automatic gain control (AGC) amplifiers, amplitudemodulators, double sideband (DSB) modulators, single sideband (SSB)modulators, AM detectors, SSB and DSB detectors, frequency doublers,squaring circuits, dividers, square-root circuits, root-mean-squaremeasuring circuits, and the like. There are also “half” Gilbert cells,which are also known as two quadrant multipliers. However, evenconventional Gilbert cells have difficulty controlling bandwidth andpeaking when integrated into a system with many other stages.

The present invention provides a modified Gilbert cell structure forimproved control of bandwidth and peaking over gain in variable gainamplifier (VGA). Further details are provided below of the device andits components are provided below.

FIG. 1 is a simplified diagram of a variable gain amplifier (VGA) deviceaccording to an embodiment of the present invention. Device 100 receivesa differential input signal having a first input signal (denoted v_(ip))and a second input signal (denoted vin); and a differential bias signalhaving a first bias signal (denoted v_(Gp)) and a second bias signal(denoted v_(Gn)). In a specific example, the differential input signalcan be a differential RF input signal. The differential bias signal canbe a differential local oscillator (LO) signal or a static differentialsignal. Further, the differential bias signal controls the gain of theGilbert cell that amplifies the differential RF input signal.

As shown, device 100 includes at least three differential transistorpairs. The first differential transistor pair includes transistorsdenoted T1 (111) and T2 (112). Each transistor includes a first node(111-a, 112-a), a second node (111-b, 112-b), and a third node (111-c,112-c); wherein the third nodes (111-c, 112-c) of each transistor in thepair are electrically coupled together. A first load resistor 131(denoted R) is electrically coupled to the second node of T2 (112-b) anda first load node 121. A first load inductor 141 (denoted L) iselectrically coupled to the first load node 131 and a power supply rail101.

The second differential transistor pair includes transistors denoted T3(113) and T4 (114). Similarly, each transistor includes a first node(113-a, 114-a), a second node (113-b, 114-b), and a third node (113-c,114-c); wherein the third nodes (113-c, 114-c) of each transistor in thepair are electrically coupled together. Also, the load configuration issimilar with a second load resistor 132 (also denoted R) electricallycoupled to the second node of T3 (113-b) and a second load node 122, aswell as and a second load inductor 142 (also denoted L) electricallycoupled to the second load node 122 and the power supply rail 101. In aspecific example, the device 100 can further include a first isolationresistor 133 (denoted R_(iso)) electrically coupled between the secondnode of T1 (111-b) and the second load node 122, and a second isolationresistor 134 (also denoted R_(iso)) electrically coupled between thesecond node of T4 (114-b) and the first load node 121.

The cross-coupling configuration is such that the second node of T4(114-b) is electrically coupled to the first load node 121 and thesecond node of T1 (111-b) is electrically coupled to the second loadnode 122. The second node of T2 (112-b) and the second node of T3(113-b) form differential output nodes denoted v_(op) and v_(on).Traditionally, the current components that run through T1 and T4 are“dumped” to the power supply rail 101. With the load resistors (131,132) and load inductors (141, 142), this configuration results in a“half” Gilbert configuration on each of the load resistors (131, 132)and a “full” Gilbert configuration on each of the load inductors (141,142). The result is higher bandwidth and peaking at high gain comparedto low gain.

Each component of the differential bias signal is fed into onetransistor (T2, T3) of each of the two differential transistor pairs inthe cross-coupled configuration. The first node of T2 (112-a) iselectrically coupled to the first node of T3 (113-a), and the first biassignal v_(Gp) is electrically coupled to the first node of T2 (112-a)and the first node of T3 (113-a). The first node of T1 (111-a) iselectrically coupled to the first node of T4 (114-a), and the secondbias signal v_(Gn) is electrically coupled to the first node of T1(111-a) and the first node of T4 (114-a).

The third differential pair provides the input signal in differentialcurrent form for the cross-coupled differential pairs discussedpreviously. The third differential transistor pair includes transistorsdenoted T5 (115) and T6 (116), and, similar to the other pairs, eachtransistor includes a first node (115-a, 116-a), a second node (115-b,116-b), and a third node (115-c, 116-c). Here, the third nodes (115-c,116-c) of each transistor in the pair are electrically coupled to acurrent source node 123, and a current source 150 (denoted i) iselectrically coupled between the current source node 123 and ground 102.Also, the first input signal v_(ip) is electrically coupled to the firstnode of T5 115-a, and the second input signal vin is electricallycoupled to the first node of T6 116-a. In a specific example, a firstdegeneration resistor 135 (denoted R_(d)) can be electrically coupledbetween the third node of T5 (115-c) and the current source node 123,and a second degeneration resistor 136 (also denoted R_(d)) can beelectrically coupled between the third node of T6 (116-c) and thecurrent source node 123. These degeneration resistors are used tolinearize the gain of the VGA, and can be configured as emitterdegeneration resistors, source degeneration resistors, or the like.

By cross coupling the T1 and T4 current to the load inductors (i.e.,“full” Gilbert configuration), the effect of the load inductors iseffectively reduced at low gain. The output voltage on the R load 132,i.e., v_(op), is determined by Rαi_(s), where R is the value of theresistor R, α is the current steering factor of the Gilbert (which isset by v_(Gp)-v_(Gn); here it is α−(1−α)=2α−1), and i_(s) is the currentfrom current source 150. Further, R+sL represents the cross-coupled loadconfiguration in the present invention. Thus, the α term is controllingthe gain of the VGA, which is shown as the current components that runthrough T2 and T3. As stated above, the current components that runthrough T1 and T4 (both denoted 1−α) just run to the power supply rail102 in conventional examples. In the present configuration,v_(op)=[Rα+sL(2α−1)]i_(s).

In an example of the present invention, the tap point into the inductorcan be chosen as another variable β, where 0<β<1, which changes the loadinductance to further “tune” the bandwidth and peaking over gain (a).According to an example of the present invention, L_(eff)=[α(1+β)−β]L.When β=1→L_(eff)=(2α−1)L. When β=0→L_(eff)=αL. The tap points 151 and152 are shown by the dotted lines denoted β in FIG. 1. When incorporatedinto a system with many stages, this “tuning” provides another means(using both L and β) of mitigating effects on gain and peaking.

In a specific example, each of the transistors is a bipolar junctiontransistor (BJT), with the first node being a base node, the second nodebeing a collector node, and the third node being an emitter node. Inanother example, each of the transistors is a field effect transistor(FET), with the first node being a gate node, the second node being adrain node, and the third node being a source node. Those of ordinaryskill in the art will recognize other variations, modifications, andalternatives.

FIG. 2 is a simplified graph of gain (A) over current steering factor(a) illustrating the characteristics of a VGA device according to the anexample of the present invention. As discussed above,v_(op)=[Rα+sL(2α−1)]i_(s) in the present configuration of the resistiveand inductive loads. Graph 200 shows the effect of gain G on α and theeffective inductance of L (L_(eff)). For example, at half gain (A=0.5),α=0.5 and L_(eff)=0. This illustrates why with the R+sL load results ina higher bandwidth at high gain as opposed to low gain.

FIG. 3 is a simplified graph illustrating a simulation of a VGA withgain dependent inductive peaking according to an example of the presentinvention. More specifically, graph 300 shows normalized amplifieroutputs at different gain levels for a conventional ideal amplifier 301(solid lines) and for an amplifier with gain dependent inductive peaking302 (dotted lines) according to an example of the present invention. Asshown, the present amplifier with gain dependent inductive peakingexhibits greater changes in peaking over gain compared to theconventional amplifier with fixed inductive peaking. The lowered peakingat low gain becomes useful for mitigating peaking effects from havingmultiple stages in a communication system. For example, this effect canbe particularly useful in a transimpedance amplifier (TIA) datapath. Ofcourse, there can be other variations, modifications, and alternatives.

In an example, the present invention provides a method of controllingbandwidth and peaking over gain in a variable gain amplifier (VGA)device. The method includes providing a cross-coupled differentialamplifier configured as a Gilbert cell having differential input nodes,differential bias nodes, differential output nodes, a current sourcenode, and two cross-coupling nodes. The cross-coupled differentialamplifier includes a load resistor coupled to each of the differentialoutput nodes and one of the cross-coupling nodes, and the cross-coupleddifferential amplifier includes a load inductor coupled to the each ofthe cross-coupling nodes and a power supply rail.

In the operation of the VGA, the method includes providing a currentsource electrically coupled to the current source node, providing adifferential bias signal to the differential bias nodes, and providing adifferential input signal to the differential input nodes. These stepsresult in the VGA amplifying, by the cross-coupled differentialamplifier, the differential input signal at the differential outputnodes, wherein the output of the cross-coupled differential amplifier ischaracterized by increased bandwidth and reduced peaking at low gain. Ina specific example, the first load inductor includes a first tunable tappoint and wherein the second load inductor includes a second tunable tappoint. Then, the method further includes tuning, by the first and secondtunable tap points, the load inductors to mitigate effects on bandwidthand peaking.

Many benefits are recognized through various embodiments of the presentinvention. Such benefits include improved control of bandwidth andpeaking over gain. In a specific example, the improved amplifierconfiguration results in higher bandwidth and lowered peaking at lowgain. The effects of this configuration can be used to mitigate theeffects of other stages in a communication system on bandwidth andpeaking. Other benefits will be recognized by those of ordinary skill inthe art that the mechanisms described can be applied to othercommunications systems as well.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A variable gain amplifier (VGA) devicecomprising: a differential input signal having a first input signal anda second input signal; a differential bias signal having a first biassignal and a second bias signal; a first differential transistor pairwith transistors T1 and T2, wherein each transistor includes a firstnode, a second node, and a third node; wherein the third nodes of eachtransistor in the pair are electrically coupled together; a first loadresistor electrically coupled to the second node of T2 and a first loadnode; a first load inductor electrically coupled to the first load nodeand a power supply rail; a second differential transistor pair withtransistors T3 and T4, wherein each transistor includes a first node, asecond node, and a third node; wherein the third nodes of eachtransistor in the pair are electrically coupled together; a second loadresistor electrically coupled to the second node of T3 and a second loadnode; a second load inductor electrically coupled to the second loadnode and the power supply rail; wherein the second node of T4 iselectrically coupled to the first load node; wherein the second node ofT1 is electrically coupled to the second load node; wherein the secondnode of T2 and the second node of T3 form differential output nodes;wherein the first node of T2 is electrically coupled to the first nodeof T3; wherein the first bias signal is electrically coupled to thefirst node of T2 and the first node of T3; wherein the first node of T1is electrically coupled to the first node of T4; wherein the second biassignal is electrically coupled to the first node of T1 and the firstnode of T4; a third differential transistor pair with transistors T5 andT6, wherein each transistor includes a first node, a second node, and athird node; wherein the third nodes of each transistor in the pair areelectrically coupled to a current source node; wherein the first inputsignal is electrically coupled to the first node of T5 and the secondinput signal is electrically coupled to the first node of T6; and acurrent source electrically coupled between the current source node andground.
 2. The device of claim 1 wherein each of the transistors is abipolar junction transistor (BJT), and wherein the first node is a basenode, the second node is a collector node, and the third node is anemitter node.
 3. The device of claim 1 wherein each of the transistorsis a field effect transistor (FET), and wherein the first node is a gatenode, the second node is a drain node, and the third node is a sourcenode.
 4. The device of claim 1 further comprising a first isolationresistor electrically coupled between the second node of T1 and thesecond load node; and further comprising a second isolation resistorelectrically coupled between the second node of T4 and the first loadnode.
 5. The device of claim 1 further comprising a first degenerationresistor electrically coupled between the third node of T5 and thecurrent source node; and further comprising a second degenerationresistor electrically coupled between the third node of T6 and thecurrent source node.
 6. The device of claim 1 wherein the differentialinput signal is a differential radio frequency (RF) input signal; andwherein the differential bias signal is a differential local oscillator(LO) signal or a static differential gain control signal.
 7. The deviceof claim 1 wherein the first load inductor includes a first tunable tappoint and wherein the second load inductor includes a second tunable tappoint; wherein the first and second tunable tap points are configured toreduce peaking at low gain.
 8. The device of claim 1 wherein thedifferential output nodes are characterized by the following:v₀=[Rα+sL(2α−1)]i_(s), where v₀ is an output voltage on the first orsecond load resistor, R is the value of the first or second loadresistor, α is a current steering factor, L is the value of the first orsecond load inductor, i_(s) is the signal current generated from theinput signal v_(ip)-v_(in), and R+sL represents the load configuration.9. A variable gain amplifier (VGA) device comprising: a differentialinput signal; a differential bias signal; a cross-coupled differentialamplifier configured as a Gilbert cell having differential input nodes,differential bias nodes, differential output nodes, a current sourcenode, and two cross-coupling nodes; wherein the cross-coupleddifferential amplifier receives the differential input signal at thedifferential input nodes and includes first and second transistors, andthe first and second transistors receives the differential bias signalat the differential bias nodes; a first isolation resistor electricallycoupled between the first transistor and a first one of thecross-coupling nodes; and a second isolation resistor electricallycoupled between the second transistor and a second one of thecross-coupling nodes, wherein the cross-coupled differential amplifierincludes first and second load resistors each coupled to each of thedifferential output nodes and one of the cross-coupling nodes; whereinthe cross-coupled differential amplifier includes first and second loadinductors each coupled to the each of the cross-coupling nodes and apower supply rail; and a current source electrically coupled to thecurrent source node.
 10. The device of claim 9 wherein each of the firstand second transistors is a bipolar junction transistor (BJT), andwherein each of the differential bias nodes is a base node.
 11. Thedevice of claim 9 wherein each of the first and second transistors is afield effect transistor (FET), and wherein each of the differential biasnodes is a gate node.
 12. The device of claim 9 further comprising:third and fourth transistors receiving the different input signal at thedifferential input nodes; a first degeneration resistor electricallycoupled between the third transistor and the current source node; and asecond degeneration resistor electrically coupled between the fourthtransistor and the current source node.
 13. The device of claim 9wherein the differential input signal is a differential radio frequency(RF) input signal; and wherein the differential bias signal is adifferential local oscillator (LO) signal or a static differential gaincontrol signal.
 14. The device of claim 9 wherein the first loadinductor includes a first tunable tap point and wherein the second loadinductor includes a second tunable tap point; wherein the first andsecond tunable tap points are configured to reduce peaking at low gain.15. The device of claim 9 wherein the differential output nodes arecharacterized by the following: v₀=[Rα+sL(2α−1)]i_(s), where v₀ is anoutput voltage on the first or second load resistor, R is the value ofthe first or second load resistor, α is a current steering factor, L isthe value of the first or second load inductor, i_(s) is the currentfrom the current source, and R+sL represents the load configuration. 16.A method of controlling bandwidth and peaking over gain in a variablegain amplifier (VGA) device, the method comprising: providing across-coupled differential amplifier configured as a Gilbert cell havingdifferential input nodes, differential bias nodes, differential outputnodes, a current source node, and two cross-coupling nodes; wherein thecross-coupled differential amplifier includes first and second loadresistors each coupled to each of the differential output nodes and oneof the cross-coupling nodes; wherein the cross-coupled differentialamplifier includes first and second load inductors each coupled to theeach of the cross-coupling nodes and a power supply rail; providing acurrent source electrically coupled to the current source node;providing a differential bias signal to the differential bias nodes;providing a differential input signal to the differential input nodes;and amplifying, by the cross-coupled differential amplifier, thedifferential input signal at the differential output nodes, wherein theoutput of the cross-coupled differential amplifier is characterized byincreased bandwidth and reduced peaking at low gain; and wherein thefirst load inductor includes a first tunable tap point and wherein thesecond load inductor includes a second tunable tap point and furthercomprising tuning, by the first and second tunable tap points, the loadinductors to mitigate effects on bandwidth and peaking.
 17. The methodof claim 16 wherein the differential input signal is a differentialradio frequency (RF) input signal; and wherein the differential biassignal is a differential local oscillator (LO) signal or a staticdifferential gain control signal.
 18. The method of claim 16 wherein theoutput of the cross-coupled differential amplifier is characterized bythe following: v₀=[Rα+sL(2α−1)]i_(s), where v₀ is an output voltage onthe first or second load resistor, R is the value of the first or secondload resistor, α is a current steering factor, L is the value of thefirst or second load inductor, i_(s) is the signal current generatedfrom the input signal v_(ip)-v_(in), and R+sL represents the loadconfiguration.